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Macros</h2></td></tr>
<tr class="memitem:ga136faa5126867cb31bb12cec43fb20a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axiethernet__v5__0.html#ga136faa5126867cb31bb12cec43fb20a2">XAxiEthernet_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + (RegOffset))))</td></tr>
<tr class="separator:ga136faa5126867cb31bb12cec43fb20a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga048aa7d7b16bc7fa5e85071bd16147aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axiethernet__v5__0.html#ga048aa7d7b16bc7fa5e85071bd16147aa">XAxiEthernet_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td></tr>
<tr class="separator:ga048aa7d7b16bc7fa5e85071bd16147aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Ethernet registers offset</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Reset and Address Filter (RAF) Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XAE_RAF_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit Pause Frame Register (TPF) bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit Inter-Frame Gap Adjustement Register (TFGP) bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Status/Enable/Mask Registers bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The bit definition of these three interrupt registers are the same.</p>
<p>These bits are associated with the XAE_IS_OFFSET, XAE_IP_OFFSET, and XAE_IE_OFFSET registers. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">TPID Register (TPID) bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Receive Configuration Word 1 (RCW1) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmitter Configuration (TC) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Flow Control Configuration (FCC) Register Bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Ethernet MAC Mode Configuration (EMMC) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">RGMII/SGMII Configuration (PHYC) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">MDIO Management Configuration (MC) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">MDIO Management Control Register (MCR) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">MDIO Interrupt Enable/Mask/Status Registers bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The bit definition of these three interrupt registers are the same.</p>
<p>These bits are associated with the XAE_IS_OFFSET, XAE_IP_OFFSET, and XAE_IE_OFFSET registers. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Ethernet Unicast Address Register Word 1 (UAW1) Register Bit</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>definitions </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Filter Mask Index (FMI) Register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Extended multicast buffer descriptor bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Ethernet Multicast Address Register Word 1 (MAW1)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Other Constant definitions used in the driver</div></td></tr>
<tr class="memitem:ga9c879203604f0d99effc88d231fd3709"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axiethernet__v5__0.html#ga9c879203604f0d99effc88d231fd3709">XAE_RST_DELAY_LOOPCNT_VAL</a>&#160;&#160;&#160;200</td></tr>
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